The present invention relates to a nonvolatile semiconductor memory device having a redundant function of relieving a defective portion inside a memory cell array by substituting a reserved or relief portion (redundancy) for the defective portion, and in particular, to an address data storage circuit incorporated in such a nonvolatile semiconductor memory device for storing the address data of the defective portion and a method of writing the address data of the defective portion to the storage circuit.
In connection with nonvolatile semiconductor memory devices, there is a known method for replacing defective bit lines, defective word lines and defective memory cells with reserved ones (redundancy) to increase the yield. In the nonvolatile semiconductor memory device utilizing such a method, the addresses of the defective bit lines, the defective word lines and the defective memory cells, i.e., the defective address data are required to be stored.
Conventionally, methods for storing the defective address data typically employ a fuse, as disclosed in, for example, the Japanese Patent Laid-Open Publication No. HEI 6-150689. FIG. 9 shows one example of a defective address data storage circuit employing a fuse. This figure shows the case where 3-bit address data is stored.
In this circuit, assuming that the address of the defective bit is 101, then the second fuse F1 is cut. Identification of the defective bit (defective address) and cutting of the fuse are performed during the device test.
Reference is next made to the case where the device actually operates after the completion of the test. If a power voltage Vcc rises, then a signal rdcamen comes to have a "high" level, and a transistor Tr that receives this signal as an input to its gate is turned on. In this stage, the first fuse F0 and the third fuse F2 are each conductive. Therefore, a voltage Vss is supplied to the inputs of the corresponding inverters In0 and In2, and output terminals radd0 and radd2 of the inverters come to have a "high" level. On the other hand, with regard to an output signal from a terminal radd1, because the fuse F1 has been cut, the input of the corresponding inverter In1 is provided with a voltage of Vcc via a capacitor C, and the output comes to have a "low" level. The corresponding p-channel MOS transistor P is turned on, so that the "low" level is latched. Consequently, data of 101 is output from the output terminals radd0 through radd2.
The most serious problem of this method is the layout area of the fuse portions. In accordance with the increase in integration density and the consequent increase in number of addresses to be stored, the layout area of these portions is inevitably increased. Therefore, the area is required to be reduced.
As a measure for solving this problem, there is a method of employing an electrically programmable nonvolatile semiconductor memory device in place of the fuse, as disclosed in, for example, the Japanese Patent Laid-Open Publication No. HEI 5-276018. FIG. 10 shows a circuit diagram of an example for storing a 3-bit address employing this method. As is apparent from FIG. 10, nonvolatile semiconductor memory cells M0 through M2 having electrically erasable programmable floating gates are arranged in place of the fuses shown in FIG. 9. In this case, instead of the cutting of the fuses, programming of the nonvolatile semiconductor memory cells is required. For this reason, a column decoder (not shown) for selectively turning on transfer gates Tr0, Tr1 and Tr2 by bit line selection signals bitse10, bitse11 and bitse12, a data latch circuit LAT for writing defective address data and a level shifter HV are added to the circuit.
Reference is then made to the case where the address 101 is stored into this circuit. The circuit shown in FIG. 10 is adapted for a flash memory which is programmed by means of channel hot electrons, as represented by ETOX (EPROM Thin Oxide). In the flash memory of this type, the threshold value of the memory cell in the initial state is about 1 V to 2 V.
The programming, or writing is performed by using channel hot electrons. A defective address is serially output to a data line DL in FIG. 10. First, a "high" level signal corresponding to the first "1" of the defective address 101 is output to the data line DL. This signal is inverted by the write data latch circuit LAT and latched. Then, a "low" level signal is supplied to the level shifter HV, and the level shifter HV outputs 0 V. As a result, the transfer gate Tr3 is turned off.
On the other hand, a voltage Vpp (10 V, for example) is applied to a word line WL of the memory cells. Then, to write to the memory cell M0, the signal bitse10 of the voltage Vpp is applied to the transfer gate Tr0. Therefore, the transfer gate Tr0 is turned on. However, the foregoing transfer gate Tr3 is off, and therefore, the bit line BL0 is placed in a floating state. Therefore, no programming is performed in the memory cell M0, and the threshold value of the memory cell M0 remains in a low state (not higher than 2 V). In this stage, the bit lines BL1 and BL2 are also in the floating state.
In accordance with the next timing, a "low" level signal corresponding to "0" of the defective address 101 is output to the data line DL. Also, the signal bitse11 of the voltage Vpp is applied to the transfer gate Tr1, and accordingly, the transfer gate Tr1 is turned on. A "high" level (Vpp level) signal is output from the level shifter HV. Therefore, the transfer gate Tr3 is turned on to output a voltage hhprg (6 V, for example) to the bit line BL1. In this stage, the bit lines BL0 and BL2 are in the floating state. On the other hand, the voltage Vpp is applied to the word line WL. Therefore, programming of the memory cell M1 is performed by channel hot electrons, increasing the threshold value.
Subsequently, data corresponding to the last "1" of the defective address 101 is stored into the memory cell M2. This operation is similar to the aforementioned operation on the memory cell M0. As a result, no programming, or writing, of the memory cell M2 is performed, and the threshold value of the memory cell M2 is maintained in a low state.
The identification of the defective address and the writing of the defective address data to a memory cell are performed during the device test, basically in the wafer test stage. The wafer test is performed for one chip not one time but several times, at least two times as a normal temperature test and a high temperature test. Then, writing of the defective address data in a manner as described above is performed every test, which means that the writing is performed at least two times, namely at the normal temperature test and the high temperature test. In addition, the normal temperature test, for example, includes several test items, and it is a normal practice to write the defective address data each time for each test item, rather than writing the data collectively after the completion of all the tests.
Generally, the aforementioned writing is performed to memory cells connected to one word line in order for data such as the defective address and the like to be output when the device power starts, as described hereinbelow.
Reference is next made to the operation when the device is actually used after the storage of the defective address data.
First, if the power voltage is applied to the device, then the signal rdcamen rises to Vcc (3 V, for example), and the transfer gate Tr that receives this signal at its gate is turned on. Further, the word line WL also rises to Vcc, so that the memory cells M0 and M2 having a low threshold value are turned on to pull the bit lines BL0 and BL2 to the Vss level. As a result, "high" level signals as inverted are output from the output terminals radd0 and radd2.
On the other hand, the memory cell M1 is not turned on since the threshold value of the memory cell M1 has been increased. Therefore, upon turning on the power, the potential of the bit line BL1 increases from Vcc via a capacitor C1. Consequently, the output of the inverter In1 goes "low" to turn on the associated p-channel MOS transistor P, by which the input of the inverter In1 is set "high" and latched. By this operation, the defective address 101 is supplied to the inverter output terminals radd0, radd1 and radd2, similarly to the case using the fuse shown in FIG. 9.
The above has described the flash memory of the type that uses channel hot electrons.
Lately, the increasing integration density of flash memories has required to reduce the consumption of power. This requirement has been satisfied by utilizing the FN (Fowler-Nordheim) tunneling phenomenon for the write operation (programming) and erase operation (erasing). The flash memory that utilizes the FN tunneling phenomenon for both the programming and erasing is called the "FN-FN type flash memory" here. In the case where defective address data is stored by means of the FN-FN type flash memory cells, the storage circuit would be one as shown in FIG. 11, which is conceivable from the circuit diagram of FIG. 10. The operation of the circuit will be described next.
First, the memory cells are collectively erased (put into the high threshold value state) in the following manner. A voltage Vns (-8 V, for example) is applied to a common source and a substrate (well) on which the memory cells are formed. By turning off transfer gates Tr that receive the signal rdcamen and the signal rdpgen at their gates, all the bit lines BL are put into the open state. Also, a voltage Vpp (10 V, for example) is applied to a word line WL connected to the control gates of the memory cells. Thus, the FN tunneling phenomenon occurs and electrons are injected from the channel layer into the floating gate. As a consequence, the threshold voltage of the memory cells is increased to more than 4 V and the memory cells are thus put into the erased state.
Next, the defective address data is written to memory cells. The defective address is serially output to the data line DL, in accordance with the timing of which the transfer gates Tr0, Tr1 and Tr2 are turned on or off by the bit line selection signals bitse10, bitse11 and bitse12 from the column decoder (not shown).
First, the defective address data are transferred to the respective latch circuits LAT0, LAT1 and LAT2. Assuming that the defective address is 101 similarly to the aforementioned case, then the "high" level corresponding to the first data "1" is output to the data line DL. The transfer gate Tr0 is turned on by the signal bitse10, and the "high" level is latched in the latch circuit LAT0. In accordance with the next timing, the "low" level corresponding to the data "0" is supplied to the latch circuit LAT1 via the transfer gate Tr1, which is now turned on, and then latched. Subsequently, the "high" level is latched in the latch circuit LAT2.
Next, a voltage Vnn (-8 V, for example) is applied to the word line WL, and in order to increase the speed of writing to the memory cells, the voltage of the signal hhprg is raised from the preceding voltage Vcc (3 V, for example) to the voltage Vpg (5 V, for example). Also, the signal rdpgen is raised to the voltage Vpps (7 V, for example) to turn on the transfer gate Tr that receives the signal rdpgen at its gate. The "high" level is latched in the latch circuits LAT0 and LAT2, so that the voltage Vpg is output to the bit lines BL0 and BL2. By this operation, the FN tunneling phenomenon occurs on the drain side of the memory cells M0 and M2 inside the memory cell array, extracting the electrons from the floating gate to the drain side. Consequently, the threshold value is lowered to a voltage of not higher than 2 V, meaning that the programming has been achieved. On the other hand, with regard to the memory cell M1, the bit line BL1 comes to have the voltage Vss (0 V) since the "low" level is latched in the latch circuit LAT1. Therefore, no programming is performed, and the threshold value is maintained at a voltage of more than 4 V. Until this time, the transfer gate transistors Tr that receive the signal rdcamen at their respective gates are allowed to be off.
The operation of the circuit when the device is actually used after the storage of the defective address data is similar to that of the aforementioned case. If the power is supplied to the device so as to apply the voltage Vcc (3 V, for example) and Vss (0 V) to the word line WL and the common source, respectively, then the defective address data 101 is output from the output terminals radd0, radd1 and radd2.
Disturb is one of problems to be discussed in the case of the flash memory. In this case, the most serious problem is the gate disturb in the write stage.
The state of the write gate disturb in the flash memory shown in FIG. 10 is schematically shown in FIG. 12. The memory cell shown in FIG. 12 is an unselected memory cell. The control gates of unselected memory cells are connected to the same word line WL as that of the selected memory cell. Therefore, the voltage Vpp (10 V) is applied also to the unselected memory cells in the data writing (programming) stage. The sources are all connected to the common source of the voltage Vss (0 V), as is apparent from FIG. 10. On the other hand, the drains are connected to the respective bit lines in the floating state (open). The substrate (well) is shared between the selected and unselected memory cells, and is at the voltage Vss (0 V). Therefore, even the unselected memory cells are brought into a slightly written state due to an electric field across the floating gate and the substrate (well), as a consequence of which the threshold values of the unselected memory cells vary (increase in this case, causing a disturb.). If the threshold values considerably change, the erased memory cells may be erroneously read as the "written state" although they should be read as the erased state.
In the case of the channel hot electrons, the write speed per cell is about 1 .mu.s (microsecond). Therefore, even if, for example, 256 memory cells are sequentially subjected to writing according to the system in which the writing is performed cell by cell as described hereinabove, the disturb time for each cell is max. 255 .mu.s on the most severe conditions. This duration is very short as the disturb time, and the device can sufficiently stand the disturb. Accordingly, there occurs no erroneous reading ascribed to a shift of the threshold value of the memory cell.
However, in the circuit system in which the address data are collectively transferred to the latch circuit so as to execute writing of the data into the memory cells inside the memory array as shown in FIG. 11, the following problem occurs.
In the FN-FN type flash memory, the writing speed utilizing the FN tunneling phenomenon is about 1 ms (millisecond) per memory cell, the speed being much slower than that of the aforementioned channel hot electron type. An example of the gate disturb state of the flash memory executing writing utilizing the FN tunneling phenomenon is schematically shown in FIG. 13.
The memory cell shown in FIG. 13 is an unselected memory cell. The control gates of unselected memory cells are connected to the word line WL together with the selected memory cell, and therefore, the voltage Vnn (-8 V) is also applied to the unselected memory cells as well when writing the defective address data. As is apparent from the foregoing description (on the operation of the memory cell that is not subjected to writing) and FIG. 11, the bit line BL connected to the drain of the unselected memory cell has the voltage Vss (0 V), while the source of the memory cell is open (because the common source line is open). The substrate (well) is common to the selected memory cell and the unselected memory cell and is supplied with the voltage Vss (0 V). Therefore, even the unselected memory cell is brought into a slightly written state due to the electric field across the floating gate and the substrate (well), and the threshold value of the unselected memory cell changes (decreases in this case. A disturb has occurred.). If the threshold value changes greatly, the erased memory cells may be erroneously read as the "written state" although they should be read as the erased state.
The writing utilizing the FN tunneling phenomenon is about 1 ms (millisecond) per memory cell, the speed being very slow, as described hereinabove. Therefore, if, for example, 256 memory cells are sequentially subjected to writing, then the gate disturb time adds up to 255 ms (1 ms during which one memory cell is selected, and 255 ms during which the other memory cells are selected). Furthermore, if a plurality of tests (for example, the normal temperature test and the high temperature test on the wafer basis and the tests of individual items) are performed as described above, then the aforementioned gate disturb time adds up to an enormous value. Due to this very long gate disturb time, the threshold value of the memory cell disadvantageously varies. Actually, a gate disturb time of not shorter than 2 ms has caused reduction of the threshold value of some memory cells to less than 4 V, depending on the fabricating conditions.
This reduction in threshold value progresses to eventually flow a current through the memory cell when the voltage Vcc is applied to the word line WL. If the threshold value becomes lower than a threshold voltage Vth at the input of the defective address latch circuit due to this, then an output that should properly be a "low" level signal is erroneously supplied as a "high" level signal at the terminal radd, resulting in the output of the wrong defective address.